Data processor performance prediction

ABSTRACT

A method of processing data using a data processor having an operating system for performing tasks of an application programme, and a power and performance controller controlling parameters and modes of execution of the tasks by the data processor. The power and performance controller includes a performance predictor producing an estimation of required performance of the data processor for the tasks taking account of inactive periods of the tasks and adjusting the performance and power consumption of the data processor in response to the estimation. The performance predictor distinguishes for each of the tasks between: —available inactive periods of the task during which the operating system is available to continue to process the same task, and —unavailable inactive periods of the task during which the operating system is not available to continue to process the same task. A substantial improvement is obtained in quality of service, with fewer missed deadlines in performance of the tasks.

FIELD OF THE INVENTION

This invention relates to a data processing apparatus, a method forprocessing data and a computer program product.

BACKGROUND OF THE INVENTION

Power saving is a constant preoccupation, especially in portable deviceswith an internal source of energy, such as a rechargeable battery. Powerconsumption of a data processor is broadly classified as dynamic powerwhile the processor is operating (for example with component circuitsswitching), and static power while it is not operating but still powered(for example non-switching steady state or transistor-off state). Staticor leakage power dissipation also occurs when a circuit is operating,although for today's technologies this is small compared to the dynamicpower dissipation.

Various power-saving technologies have been developed to address sourcesof power waste. Many are all-hardware solutions such as smaller siliconprocess geometries, active well biasing and auto-idle detectioncircuits. Other technologies address the compromise between theoperating parameters of the data processor on one hand and powerconsumption on the other hand. One such technique is known genericallyunder the name of Dynamic power management (DPM), which describes asystem that sets the power states of its hardware modules in real timeto minimize power waste, with the minimum performance needed still tomeet operational requirements. DPM includes techniques such as dynamicvoltage and frequency scaling (DVFS) and dynamic process and temperaturecompensation (DPTC) for dynamically controlling operational modes, andidle time prediction for controlling low-power idle modes (such as doze,where the processor is powered but not clocked, and sleep, where somemodules of the processor are not supplied with operational power).

These techniques will now be reviewed in more detail. Applicationprograms and other system software are monitored during execution in thedata processor. Some of these applications can identify their comingperformance-power needs (“power aware” software) but many others cannot.Awareness of coming performance-power needs can be used to control apower manager that drives the hardware power-saving mechanisms usingsoftware drivers and power handlers in the data processor operatingsystem.

One dynamic power saving technique is to slow or disable the clock to alogic circuit when the circuit is idling. Clock gating or clock freezingsaves power not just in the registers whose clock is gated off, but alsoin combinational logic circuits connected to them, as the registersignals are no longer propagated. Clock gating is very quick to turn onand off, so software that uses such circuits should not be affected ifit is timed correctly. Static or leakage power dissipation needs moredrastic measures. One solution, called power gating, is to power off thedevice or subcomponent. Power gating reduces both dynamic and leakagepower, and can be implemented either locally on-chip or externally atthe power supply unit.

Another power-saving technique is to vary the supply voltage to acircuit either when no performance is required (idling) or when variableperformance is required. During idling mode the hardware can switchautomatically from a higher to a lower voltage when the device orsubcomponent transitions from an active state to a low-performancestate. An example is a processor core design where operating voltage isreduced automatically when it enters a sleep or stop mode. Although thecore is not clocked in this mode, it still suffers steady-state currentleakage. Because the core does not need to execute instructions or otherfunctions, the operating voltage can be lowered to a value justsufficient to ensure that internal state data is retained correctly.This is sometimes called stop mode voltage scaling.

The non-idling situation, where variable performance is needed, isaddressed by varying the operating frequency, the operating voltage, orboth. Dynamic Frequency Scaling relies on the observation that dynamicpower consumption in an integrated circuit is roughly proportional tooperating frequency. It makes sense, therefore, to lower the clockfrequency of a processor to the lowest value that still meets therequired processing performance. This means that although the softwareruns more slowly, it still meets its real-time deadlines with acceptablemargins. This is done dynamically and needs power management softwareadapted to decide which frequency setting is acceptable. Better powersavings can be achieved if the operating voltage is also scaled. Sincepower varies with the square of voltage, square-law power savingspotentially are possible with voltage scaling. If voltage scaling andfrequency scaling are both used, the combination, called dynamic voltageand frequency scaling (DVFS), can yield power savings roughlyproportional to the cube of operating voltage.

These square-law and cube-law power savings depend not only on theconfiguration and efficiency of the voltage control circuits, but alsoon the efficiency of prediction software used to set thevoltage/frequency settings. For a given integrated circuit design, theoperating voltage determines the maximum usable operating frequency. Thevoltage (and hence frequency) are scaled to trade required performanceagainst minimal power waste. When scaling the voltage up or down(thereby consuming more or less power), the operating frequency is alsoscaled, and with it the available performance of the device, which is tobe controlled to remain within the operational tolerance of the design.DVFS technology addresses varying but continuing software workloads.

Performance-prediction and performance-setting algorithms are availableto control the performance-power states of the system hardware such asthe processor speed-voltage levels dynamically, both for run modes andfor idle modes. Algorithms exist for use with DVFS-based processors thatset the processor's operating frequency and voltage based on predictingthe short-term software workload on the processor. An example algorithmin this class tracks the history of the recent software workload of eachtask (that is to say a set of program instructions that is loaded inmemory) running in the OS and extrapolates it to derive a prediction ofrequired performance in the next coming period. This technique assumes areasonable correlation between the recent past workload of a task andthat of the near future. The task status information is supplied by theOS kernel. The algorithm maintains estimates of workload and unusedidling time to predict the aggregate workload (for all tasks). Thisnormalized MCU processing level is translated by associated softwareinto the relevant frequency and voltage settings required for thespecific DVFS mechanism used. The algorithm continuously re-calculatesand supplies new predictions in response to changing software workloads.In principle, the algorithm predicts the required processor performancethat just meets individual deadlines for each OS task. The algorithmworks reasonably well for OS tasks whose workloads don't change veryrapidly.

The actual performances and power savings achieved by this kind ofalgorithm have been disappointing compared to theoretical calculationsand prototype simulations. It is an object of the present invention toimprove the achievable performances and power savings of a dataprocessor.

SUMMARY OF THE INVENTION

The present invention provides a data processing apparatus, a dataprocessing method and a computer programme for performing the dataprocessing method as described in the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an example of a data processingapparatus employing a dynamic voltage and frequency scaling (‘DVFS’)process in accordance with one embodiment of the invention, given by wayof example,

FIG. 2 is an example of a timing diagram of performance prediction in aknown DVFS process,

FIG. 3 is an example of a timing diagram of performance prediction in aDVFS process in the data processing apparatus of FIG. 1,

FIG. 4 is a flow chart of the DVFS process of FIG. 3 for a first task,and

FIG. 5 is a flow chart of the DVFS process of FIG. 3 for a second task

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 of the drawings shows a data processing apparatus 100 employing adynamic voltage and frequency scaling (‘DVFS’) process in accordancewith one embodiment of the invention, given by way of example. In thisexample, the invention is illustrated as applied to a video playerapplication but it will be appreciated that the invention is applicableto many other applications.

The apparatus 100 comprises an central processor unit (‘CPU’) 102including an operating system (‘OS’) 104, a video player applicationprogramme 106, other system software 108 for performing otherapplications and a DVFS processor 110 for setting the processor'soperating frequency and voltage based on predictions of the short-termsoftware workload on the CPU 102.

The apparatus also includes a performance predictor 112 for predictingthe performance required for each task to be completed before criticaldeadlines, the performance predictor receiving an input 114 from the OS104 regarding the task running times of the video player applicationprogramme. The performance predictor 112 produces a performance leveloutput signal 116 for each task, which it provides to DVFS hardware 118.The DVFS hardware 118 supplies signals 120 and 122 defining the selectedvoltage and clock frequency levels that the DVFS processor 110 appliesto the CPU for each task.

The performance predictor 112 predicts the short-term software workloadon the CPU for each task using an algorithm which tracks the history ofthe recent software workload of each task running in the OS andextrapolates it to derive a prediction of required performance in thenext coming period. In this embodiment of the present invention, theperformance predictor 112 is arranged to distinguish between blockingand non-blocking operating system access calls.

Input and output operations in data processing apparatus can beextremely slow compared to the processing of data. For example, during afetch operation that takes ten milliseconds to perform, a processor thatis clocked at one gigahertz could have performed ten millioninstruction-processing cycles.

A simple approach to input and output operations (‘I/O’) for a task ‘A’is to start the access and then wait for it to complete beforeprocessing task A or even other tasks. Such an approach (calledsynchronous I/O or blocking I/O) is necessary for certain types of I/Obut blocks the progress of a program while the I/O is in progress,leaving system resources idle. When a program makes many I/O operations,this means that the processor can spend almost all of its time idlewaiting for I/O operations to complete.

For some processing tasks, it is possible to start the I/O for a task Aand then perform processing that does not require that the I/O hascompleted, in particular processing of other tasks. For these othertasks, the I/O is asynchronous or non-blocking I/O. Any task, such asthe task A that actually depends on the I/O having completed (thisincludes both using the input values and critical operations that needto assure that a write operation has been completed) still has to waitfor the I/O operation to complete, and thus is still blocked, but otherprocessing tasks which do not have a dependency on the I/O operation cancontinue.

Asynchronous input/output, or non-blocking input/output of a task ‘A’,is a form of input/output processing that permits the operating systemto process other tasks before the input/output transmission hasfinished, although task A itself has to wait for the completion of theI/O. On the other hand, a call by the application on the OS resources(the CPU) for task A can block the OS even for performance of othertasks during the period of a non-blocking I/O call unless the call alsoforces the application to release the OS for the other tasks, in whichcase task A itself is then blocked by lack of OS resource.

Taking account of idle periods to calculate the required processorperformance enables the DVFS controller to adjust the performance sothat it is just sufficient to meet deadlines and other requirements. Theperformance predictor 112 in the embodiment of the present inventionshown in FIG. 1 is arranged to distinguish for a given task A between: —

-   -   inactive periods relating to a non-blocking operating system        access call where tasks other than task A can continue to be        processed while the OS call is interrupted, at least during a        waiting period where the task A requires completion of I/O        access, for example, and    -   a blocking operating system access call where the task A does        not release the OS during a waiting period where the task A        requires completion of I/O access and no tasks can be processed        after the call until completion of the operating system access.

The power and performance controller function of the apparatus of FIG. 1includes an idle time compensator which modifies the idle timecalculation of the performance predictor 112 for each task to make adistinction between inactive periods of that task where operating systemaccess was available ('unblockee) to that task and therefore denied toother tasks, on one hand, and inactive periods of that task whereoperating system access was unavailable (‘blocked ’) to that task andtherefore available to other tasks. For the inactive periods of task A,where the CPU was inactive but dedicated to task A, and thereforeblocked for other tasks, the CPU could have run slower during its activeperiod of processing task A and use part of the inactive period thatotherwise idles. On the contrary, for the inactive periods of task A,where the CPU was inactive but blocked by other tasks and thereforeunavailable to task A, it is erroneous to assume that the CPU could haverun slower during its active period, since the CPU could not have runslower during its active period in order to use part of the inactiveperiod for task A anyway. Conversely, for the inactive periods that areblocked to task A, if the CPU 102 did not process any other tasks whileit was available for those other tasks, the waiting period of each ofthose other tasks can correctly be taken into account for the othertasks (but not for task A) when calculating possible performancereduction and power consumption savings.

Specifically, the idle time compensator 124 receives signals 126, 128and 130 from the OS 104 identifying respectively whether an OS accesscall of the current application task is blocking or non-blocking for useof the CPU for other tasks, the uncorrected (‘raw’) idle time associatedwith the current task and other information relative to the currenttask. The idle time compensator 124 then subtracts from the raw idletime for each task 134 any inactive time during which the CPU was anywayunavailable to perform that same task and provides to the performancepredictor 112 outputs 132 defining the idle time calculation thusmodified for each task identified at 134.

In more detail, in this example of an embodiment of the presentinvention, the performance estimate is derived using the followingsteps. It will be appreciated that other algorithms could be used toimplement such embodiments of the invention.

First, the full-speed equivalent workload Work_(fse) of the task duringa succession of timeslots i=1 to N during a recent past period (forexample 100 ms, depending on the OS) is calculated using the equation

${Work}_{fse} = {\sum\limits_{i = 1}^{N}\; {t_{i} \times p_{i}}}$

where t_(i) is the length of the time slot i and p_(i) is the CPUperformance rate during the time slot.

Next, a decaying average of workload over a longer period is calculatedusing the following equation:

${WorkEst}_{new} = \frac{{k \times {WorkEst}_{old}} + {Work}_{fse}}{k + 1}$

where k is a weighting factor.

Then, a decaying average of the time to go to the required deadline iscalculated using the following equation:

${Deadline}_{new} = \frac{{k \times {Deadline}_{old}} + {Work}_{fse} + {Idle}_{fse}}{k + 1}$

where Idle_(fse) is the idle time for the task compensated bysubtracting idle time for which the CPU was unavailable for that task.

Lastly, the adjustment in percentage of the performance required just tomeet the calculated deadline time is calculated using the followingequation:

${Perf}_{task} = {\frac{{WorkEst}_{task}}{{Deadline}_{task}}.}$

An illustration of the effect of the idle time compensator 124 is shownin FIG. 2, which shows the functioning of a DVFS system without the idletime compensator 124 and FIG. 3, with the idle time compensator 124.

In FIGS. 2 and 3, the video application programme is shown as requiringframes of n time slots 200 to be played back from an input buffer (notshown) for a task A. Each frame is followed by a slot 202 in which theprocessing of the frames waits for a synchronisation signal and the CPUcan be inactive. In the example shown in the drawings, no other taskthan task A calls for servicing by the OS. However, during the wait fora synchronisation signal, the OS would be available to perform tasksother than task A provided the other tasks are completed by the CPUsufficiently before the next slot 200 where the next synchronisationsignal for task A requires processing in the CPU.

CPU 102 alternates between active periods 208 and inactive periods 210in which the current task is completed and the CPU is put to idle if noother task calls for servicing by the OS. The processing of video framesby the video application program 104 continues in this fashion until theinput buffer is empty. During subsequent inactive periods 204 and 206,the video application program makes a system call to the OS requesting afetch of new frame data that is not already in the local input buffer,and the OS is unavailable to process the task A whilst the I/O interface(for example a network driver or disk driver) fetches the data from theinput into the buffer. This deferred completion is an asynchronousoperation in that sense. The OS 104 returns control to the calling videoprogram which completes its work on the current frame then yieldscontrol to the OS at the end of slot 200. Slot 200 corresponds to theDVFS Processor 110 being active (e.g. in Run mode). The task A cannotuse the CPU during the inactive periods 204 and 206, where the OS isunavailable to process data for task A. The task A can resume as soon asdata is available in the buffer provided no other task has blocked theCPU in the meantime.

The action of the performance controller, including the performancepredictor 112, the voltage and frequency setting hardware 118 and theDVFS processor 110 in the absence of the idle time compensator 124 isillustrated in FIG. 2. As shown by the graph 212 of frequency (and/orsupply voltage) against time, initially the CPU runs at normal speed,with full clock frequency. After two inactive periods 210, thecalculation of performance required leads the performance controller toslow the CPU 102, as shown at 214, so that the active period of the CPUruns at slower speed for a longer time, with corresponding energysaving, reducing the duration of the idle period. The active periods ofthe task A are still completed satisfactorily before the slot deadlines,shown at 216.

However, when the input buffer is empty, and the process calls for afetch of further data from the input into the buffer at 204 and 206, theperformance controller again reduces the speed of the CPU performance,as shown at 218, since all the OS inactive periods of the current task Aare taken into account in calculating the performance required,including the idle periods 220 during which the CPU could not processtask A while data is being fetched into the buffer. In fact, theperformance controller underestimates the performance required fortimely completion of the task once data is available for the task tostart again. When the data is available and the CPU 102 resumes anactive slot at 222, the duration of the active period is prolonged toomuch and the deadline 224 for completing the active period is overshot.In practice, it is found that such missing of deadlines leads tosub-optimal behaviour of the system and in particular to lack ofstability and inaccurate prediction. This results in degraded quality ofservice such as, in a video player application, missed video frames, forexample. Such sub-optimal behaviour is not apparent from typicalmodelling of the process in relatively stable workload conditions norfrom simple non-OS testing of the workload and performance predictor.

Turning now to FIG. 3, which shows the functioning of the DVFS systemwith the idle time compensator 124, similar elements are indicated bythe same reference numbers as in FIG. 2. The same reduction of speed ofthe CPU performance occurs at 214, due to the blocking idle periods 202.However the idle time compensator 124 corrects the raw idle timeindication 128, so that the modified idle time indication now ignoresthe idle times 220 which are anavailable to task A. As a result, theperformance controller correctly does not make a further reduction inspeed of the CPU 102 at 226 in response to the idle periods 220 and theCPU runs at unchanged speed during the following active period 228, sothat it is completed before the deadline 224. In actual usage of the CPUwith such practical applications, it is found that a substantialimprovement is obtained in avoiding missed deadlines, so that the systemstability and quality of service are greatly improved in practical usagecases, even though modelling and testing do not necessarily reveal theimprovement.

FIGS. 4 and 5 illustrate an example of the sequencing of process stepsbetween the video player programme 106, the kernel of the OS 104 and theperformance controller modules including the DVFS processor 110, theperformance predictor 112, the DVFS hardware 118 and the idle timecompensator 124. FIG. 4 shows the process in the case of a validvoltage/frequency calculation as shown at 214 in FIGS. 2 and 3 and at226 in FIG. 3, and FIG. 5 shows the process in the case of an invalidvoltage/frequency calculation as shown at 218 in FIG. 2.

Referring first to FIG. 4, the process 400 illustrated starts withdecoding a frame at 402 and sending the decoded frame to the display at404, corresponding to the playback n steps 200 of FIGS. 2 and 3. At theend of the frame, the video player application then sleeps waiting for asynching stream at 406. A scheduler in the OS kernel 104 responds at 408to the video player application sleeping by noting the absence of aprocess to run in the run queue and at 410 schedules an idle period,economising consumption of energy, corresponding to the idle steps 202of FIGS. 2 and 3. The idle time i1 is identified at 412 and sent to theidle time compensator 124. The idle time compensator 124 verifies at 414that the idle time is a time where the OS was available for processingtask A, and is not a time where task A is waiting for an I/O, and sendsa signal to the scheduler in the OS kernel 104 at 416. In thisembodiment of the invention, the idle time compensator takes account ofthe reason why the period is inactive when distinguishing betweenavailable inactive periods where the OS was available for the currenttask A and unavailable inactive periods where it was not.

The scheduler picks the next runnable task at 418 and identifies thistask to the performance predictor 112 through the idle time compensator124. The performance predictor 112 computes the appropriatefrequency/voltage for that task at 420, including information about idleperiod i1 from step 414 into the decaying average idle time accumulatorfor the tasks, and defines the corresponding task run time and idle timeat 422. The video player application can then instruct the OS to startdecoding the next frame at 424 and sending the decoded frame to thedisplay at 426.

In the process shown in FIG. 5, the process illustrated starts with thevideo player application 106 arriving at a state 502 where it hasfinished processing all frames from its input buffer, which is empty andthe player has to call the network driver to fetch new frames,corresponding to the end of the playback step before the waiting steps204 and 206 of FIGS. 2 and 3. The OS kernel 104 responds to thissituation at 506 by putting the task A into a wait queue for the networkdriver. At 508, in this example, the OS kernel 104 has no other tasks torun at this point in time and schedules an idle period i2 for the CPU at510, economising consumption of energy, corresponding to the idle steps204 and 206 of FIGS. 2 and 3. The idle time i2 would be exploitable forother tasks but the OS is unavailable for task A, whether or not itprocesses other tasks. The idle time i2 is identified at 512 and sent tothe idle time compensator 124. The idle time compensator 124 verifies at514 that the idle time is available for task A and sends a signal to thescheduler in the OS kernel 104 at 516 when data is ready for task A.This triggers the scheduler at 518 to pick the next runnable task at 520and to identify this task to the performance predictor 112 through theidle time compensator 124. The performance predictor 112 computes theappropriate frequency/voltage for task A and the other tasks at 522,eliminating idle period i2 from the decaying average idle timeaccumulator for task A due to the information from step 514, butincluding information about idle period i2 from step 514 into thedecaying average idle time accumulator for the other tasks. Theperformance predictor 112 defines the corresponding task run time andidle time at 524 and this data is passed to the video playerapplication, which starts decoding the next frame at 526 and sending thedecoded frame to the display at 528.

The embodiments of the invention shown in the drawings are simpleprocesses that illustrate features of the embodiments. It will beappreciated that these embodiments of the invention are applicable toadvanced runtime performance algorithms and can use standardizedsoftware framework that supports multiple concurrent predictors,policies and power cost rules, for example. These embodiments of theinvention can run with the system software of various commerciallyavailable operating systems

1. Data processing apparatus comprising: a data processor having anoperating system for performing tasks of an application programme; and apower and performance controller for controlling parameters and modes ofexecution of said tasks by said data processor, said power andperformance controller including a performance predictor for producingan estimation of required performance of said data processor for saidtasks taking account of inactive periods of said tasks and adjusting theperformance and power consumption of said data processor in response tosaid estimation; wherein said performance predictor being arranged todistinguish for each of said tasks between: — available inactive periodsof said data processor during which said data processor was available toprocess the same task, which are included in producing said estimationof required performance for the same task, and unavailable inactiveperiods during which the same task was not available for processing andsaid data processor was not available to process other tasks, andunavailable active periods of said data processor during which said dataprocessor was not available to process the same task but was processingother tasks, which are excluded in producing said estimation of requiredperformance for the same task.
 2. Data processing apparatus as claimedin claim 1, wherein said data processor is responsive to unavailableinactive periods for a task to switch the operating system to anothertask if not blocked by the inactive task, or to an idle mode if no othertask is ready to be processed.
 3. Data processing apparatus as claimedin claim 1, wherein said power and performance controller is responsiveto said available inactive periods but not to said unavailable periodsfor a task in producing said estimation for that task.
 4. Dataprocessing apparatus as claimed in claim 1, wherein said tasks includeinput/output accesses, and said power and performance controller isresponsive to said input/output accesses of a task to excludecorresponding inactive periods in producing said estimation for thattask.
 5. Data processing apparatus as claimed in claim 1, wherein saidpower and performance controller is responsive to a decaying average ofworkload for a task in producing said estimation for that task.
 6. Dataprocessing apparatus as claimed in claim 1, wherein said power andperformance controller is arranged to adjust clock frequency and orsupply voltage for said data processor in adjusting the performance andpower consumption of said data processor in response to said estimation.7. A method of processing data using a data processor having anoperating system for performing tasks of an application programme, and apower and performance controller controlling parameters and modes ofexecution of said tasks by said data processor, said power andperformance controller including a performance predictor; the methodcomprising: producing by said performance predictor an estimation ofrequired performance of said data processor for said tasks takingaccount of inactive periods of said tasks; and adjusting by saidperformance predictor the performance and power consumption of said dataprocessor in response to said estimation distinguishing, by saidperformance predictor for each of said tasks between: — availableinactive periods of said data processor during which said data processoris available to continue to process the same task, and unavailableinactive periods during which the same task was not available forprocessing and said data processor was not available to process othertasks, and unavailable active periods of said data processor duringwhich said data processor was not available to process the same task butwas processing other tasks, which are excluded in producing saidestimation of required performance for the same task.
 8. A method ofprocessing data as claimed in claim 7, wherein said data processor isresponsive to unavailable inactive periods for a task to switch theoperating system to another task if not blocked by the inactive task, orto an idle mode if no other task is ready to be processed.
 9. A methodof processing data as claimed in claim 7, wherein said power andperformance controller responds to said available inactive periods butnot to said unavailable periods for a task in producing said estimationfor that task.
 10. A method of processing data as claimed in claim 7,wherein said tasks include input/output accesses, and said power andperformance controller responds to said input/output accesses of a taskto exclude corresponding inactive periods in producing said estimationfor that task.
 11. A method of processing data as claimed in claim 1,wherein said power and performance controller responds to a decayingaverage of workload for a task in producing said estimation for thattask.
 12. A method of processing data as claimed in claim 1, whereinsaid power and performance controller adjusts clock frequency and orsupply voltage for said data processor in adjusting the performance andpower consumption of said data processor in response to said estimation.13. (canceled)
 14. Data processing apparatus as claimed in claim 2,wherein said power and performance controller is responsive to saidavailable inactive periods but not to said unavailable periods for atask in producing said estimation for that task.
 15. Data processingapparatus as claimed in claim 2, wherein said tasks include input/outputaccesses, and said power and performance controller is responsive tosaid input/output accesses of a task to exclude corresponding inactiveperiods in producing said estimation for that task.
 16. Data processingapparatus as claimed in claim 3, wherein said tasks include input/outputaccesses, and said power and performance controller is responsive tosaid input/output accesses of a task to exclude corresponding inactiveperiods in producing said estimation for that task.
 17. Data processingapparatus as claimed in claim 2, wherein said power and performancecontroller is responsive to a decaying average of workload for a task inproducing said estimation for that task.
 18. Data processing apparatusas claimed in claim 3, wherein said power and performance controller isresponsive to a decaying average of workload for a task in producingsaid estimation for that task.
 19. Data processing apparatus as claimedin claim 4, wherein said power and performance controller is responsiveto a decaying average of workload for a task in producing saidestimation for that task.
 20. Data processing apparatus as claimed inclaim 2, wherein said power and performance controller is arranged toadjust clock frequency and or supply voltage for said data processor inadjusting the performance and power consumption of said data processorin response to said estimation.
 21. Data processing apparatus as claimedin claim 3, wherein said power and performance controller is arranged toadjust clock frequency and or supply voltage for said data processor inadjusting the performance and power consumption of said data processorin response to said estimation.